With an increasing scale of data processing chips, there are more on-chip memories. To reduce a scale of memories, shared caches are used in some cases in which whole-thread caches are not needed, so as to reduce memory resources. Therefore, resource management of shared caches is particularly important.
FIG. 1 is a block diagram of basic implementation of a shared cache. As shown in FIG. 1, after a command (such as read, write, add, subtract, search, or flow control) from an ATOM (a programmable processor) enters an input processing module, the input processing module parses the command to confirm whether the command needs cache data. If the command needs cache data, the input processing module sends a cache application to a cache management module. The cache management module searches a bitmap table, and if the bitmap table indicates that there is an idle cache unit (that is, there is a cache unit labeled as 1 in the bitmap table), the cache management module allocates an idle cache unit and feeds back a cache address of the cache unit to the input processing module. In this step, an indication in the bitmap table that corresponds to the allocated cache unit further needs to be labeled as that the cache unit is occupied (that is, the indication in the bitmap table that corresponds to the cache unit is labeled as 0), as shown in FIG. 2. The input processing module stores, according to the returned cache address, associated information that does not participate in data processing, such as a thread identity (IDentity, ID for short) of the command, in a shared cache, and sends the cache address and the command together to a command processing module for data processing. In the whole processing process, the associated information of the command is stored in the shared cache throughout. After command processing ends, the command processing module sends a processing result and the cache address to an output processing module. The output processing module reads out the associated information in the shared cache according to the cache address and sends the cache address to the cache management module for cache recycling, and then the indication in the bitmap table that corresponds to the cache address is labeled as that the cache unit is not occupied (that is, the indication in the bitmap table that corresponds to the cache unit is labeled as 1), as shown in FIG. 1. Finally, the output processing module sends the command processing result and cache data together.
Further, a data processing module further includes a first in first out (First Input First Output, FIFO for short) queue, a crossbar (Crossbar), a scheduler (Scheduler) and the like. Therefore, if an error checking and correcting (Error Correcting Code, ECC for short) error or a parity error occurs in data in a whole path of the data processing module, a cache address and a whole command are untrusted. Consequently, the command is lost. As a result, no corresponding cache address is sent to the output processing module, and then the cache management module cannot receive a cache address sent from the output processing module. Consequently, a cache unit corresponding to the cache address is always being occupied, which causes a cache unit leakage (until a system is reset or the bitmap is initialized).
Therefore, as a runtime of the system becomes longer, available cache space inevitably becomes smaller due to the cache unit leakage, which then lowers a bandwidth and performance of the system.